PUBLICATIONS IN REFEREED JOURNALS and ARTICLES:
- Zyarah, Abdullah M. “Design and Analysis of a Reconfigurable Hierarchical Temporal Memory Architecture.” (2015).
PUBLICATIONS IN CONFERENCES:
Zyarah, Abdullah M., Nicholas Soures, Lydia Hays, Robin B. Jacobs-Gedrim, Sapan Agarwal, Matthew Marinella, and Dhireesha Kudithipudi. “Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks.” In Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, pp. 1-4. IEEE, 2017.
- Zyarah, Abdullah M., and Dhireesha Kudithipudi. “Resource Sharing in Feed Forward Neural Networks for Energy Efficiency.” Circuits and Systems (MWSCAS), 2017 IEEE 60th International Midwest Symposium on
Soures, Nicholas, Lydia Hays, Eric Bohannon, Abdullah M. Zyarah, and Dhireesha Kudithipudi. “On-Device STDP and Synaptic Normalization for Neuromemristive Spiking Neural Network.” Circuits and Systems (MWSCAS), 2017 IEEE 60th International Midwest Symposium on.
- Abdullah M. Zyarah, and Dhireesha Kudithipudi. “Extreme learning machine as a generalizable classification engine.” In Neural Networks (IJCNN), 2017 International Joint Conference on, pp. 3371-3376. IEEE, 2017
- Abdullah M. Zyarah, Abhishek Ramesh, Cory Merkel, Dhireesha Kudithipudi, “Optimized hardware framework of MLP with random hidden layers“, Proc. SPIE 9850, Machine Intelligence and Bio-inspired Computation: Theory and Applications X, 985007 (May 12, 2016); doi:10.1117/12.2225498.
- Abdullah M. Zyarah, Dhireesha Kudithipudi, “Reconfigurable Hardware Architecture of the Spatial Pooler of Hierarchical Temporal Memory“, 2015 28th IEEE International System-on-Chip Conference (SOCC) – Emerging and Evolutionary Design; 09/2015.