Lesson-1- Introduction to FPGA and VHDL


1.1 Introduction:
This is the first tutorial in the series “Learn how to use FPGA”. In these lessons, we will learn how to use VHDL, hardware description language, along with the FPGA to build simple and sophisticated digital systems. Qurtus Altera tools can be used with these tutorial since its free and available online to anyone to download (No license required for webpack version). Personally, I prefer ISE Xilinx tools, but it is not free. The student can download the webpack version of ISE for free, but the student version has limitation to the version of Xilinx FPGA that can be accessed. One of the great merits of using VHDL is that, the VDHL is a standard language and this means the code will be tools independent. Thus, do not worry too much about the tools, use the tools that meet your needs and makes you comfortable.
In the lessons that I started today, two models will be presented and discussed in each post. The first one includes the circuit required to be implemented, and the second model will be the test-bench that has all the necessary data required to verify whether the implemented circuit performs the intended function and meets the performance goals.


1.2: Introduction to FPGA:
The digital devices can be classified into two main groups: ASICs (Application Specific Integrated Circuit) and standard digital devices. Our concentration in these lectures will be on ASICs devices and specifically on FPGA (Field Programmable Gate Array). The FPGA can be defined as a specialized integrated circuit that can be programmed by user for a particular purpose. Basically, its architecture is composed hundreds of small blocks that is named as a configurable logical blocks (CLB) and a network of interconnects that can be used to connect these CLBs together based on the mapped design and the intended use. Each CLB has small size SRAMs (two or more) known as look-up table (LUTs), Multiplexers, Multipliers (optional), Adders, and other units based on the utilized FPGA family. The figure below shows the general architecture of an FPGA with a detailed representation for the CLBS and interconnects.

FPGA Architecture

FPGA Architecture Ref.


1.3: Configurable Logic Block Architecture:
The CLB in its basic form has three main units, LUT to store the output of a particular functional unit, storage element (FF), and a mux to select the proper route to the output of the CLB. Let us consider the following example to see how a logical unit is mapped to CLB. If it is needed to map a 2-input AND gate to the CLB below:

  • The output of the AND gate for all possible inputs will be store in the LUT.
  • The input of the AND gate is used as a memory address pointer that selects the functional value which can be available at the CLB block output. In the given example, “00” address will point to the first location in the memory which has a value of ‘0’, and “11” will refer to the fourth location in the memory that holds ‘1’, and so on.
  • Then, the output of the LUT will be routed out of the CLB via the mux, or through the FF and the mux for subsequent use.

Basic CLB Architecture Ref.


1.2: Introduction to VHDL:
HDL is a hardware description language that can be used to describe a custom digital hardware. Unlike other languages (such as C, Java, etc.), HDL does not simply include writing the code and letting the tools optimize it. The efficient description of the design is really significant to achieve an efficient implementation. One of the main differences between the HDL and other conventional languages is the concurrency in executing the statements. This is determined by the flow of the signal rather than the textual order. In the next lecture, we start coding the first VHDL code to get familiar with the VHDL syntax and the language constructs.